Host selectively determines whether a task should be performed by digital signal processor or DMA controller according to processing time and I/O data period

ABSTRACT

A low-cost digital signal processing system is provided which can prevent data loss during data transfer and can eliminate processing overhead regardless of the length of the I/O period of an external I/O processing device. When the data I/O period of the external I/O device such as an A/D converter is shorter than the period of data processing by the DSP, the data reception and transmission are performed through a DMA controller between the external I/O devices and the memory to reduce the burden on the DSP. On the other hand, when the data input and output period is longer than the DSP processing time, the data reception and transmission is directly carried out by the external I/O device and the DSP without use of the DMA controller. In addition, in the execution of a DSP program which comprises at least one process, a function of each process is provided to have input and output parameters identifying the addresses of data reception or transmission units which are assigned to the input and output parameters to simplify the DSP programming.

FIELD OF THE INVENTION

This invention relates to an I/O technique for a digital signalprocessing system, and more particularly, to a technique forsubstantially eliminating data loss during data access to/from anexternal I/O device without additional processing overhead.

BACKGROUND OF THE INVENTION

A test system for examining the characteristics of an IntegratedServices Digital Networks (ISDN), an A/D converter and the like performsdigital calculations such as Fourier transformation, Fourierinverse-transformation and other filtering functions. In order toincrease the processing speed, a digital signal processor, hereinafterreferred to as "DSP", has been used.

FIG. 1 schematically illustrates an embodiment of a multi-processor typesignal processing system which comprises three DSP units 30A, 30B, 30Cand a CPU 1 for controlling these units. The units 30A, 30B, and 30C arerespectively equipped with DSPs 31A, 31B, and 31C, memories 32A, 32B,and 32C and external I/O devices 33A, 33B and 33C. During operation, inthe unit 30A, for example, I/O data is accessed from the I/O device 33Aand is then sent to the DSP 31A and subjected to processing such asFourier transformation. The processed data is then transferred to theunit 30B through a peripheral I/O interface (not shown) and subjected tofurther processing such as filtering in the DSP 31B. The processed datais then transferred to the unit 30C through a peripheral I/O interface(also not shown). The processed data is then subjected to a furtherprocessing such as Fourier inverse-transformation by the DSP 31C, andthe processed result is transferred to external I/O device 33C foroutput.

In addition to executing a high-speed processing program, the DSPgenerally has other functions for executing various processes. Thesetasks include access to the external I/O devices for receiving data fromvarious output devices such as an A/D converter, a D/A converter,various types of peripheral I/O interfaces, etc., and for transferringthe computed data to other external I/O devices. The following methodshave been known for transferring data during reception and transmissionto/from external I/O devices: (1) the data receiving and transmittingoperations are carried out through an interrupt to the computer programof the DSP; and (2) with no interrupt, the data is temporarily stored inan external register file and then the data reception and transmissionare successively carried out.

FIG. 2 is a schematic circuit diagram of an embodiment of a conventionaldigital signal processing system utilizing the method (1). In FIG. 2, aDSP 2 controls an access to a memory 5, an A/D converter 3, and aperipheral I/O interface 4 through common busses such as data bus 6 andaddress bus 7. A decoder 8 is further provided in the address bus 7 tooutput an enable signal to the A/D converter 3 and the peripheral I/Ointerface 4. In addition, through the common system bus, the CPU 1performs various processing including controlling the DSP 2, loadingdown the DSP program to the memory 5, and so on.

The DSP 2 runs a DSP program in the memory 5 which serves as a real-timemonitor. Instructions for the DSP 2 are programmed in the real-timemonitor in such a manner that a series of signal processing blocks areconstructed as a processing task. These programs are executed under themanagement of a scheduler. However, the I/O processing is carried out asa different task from the above task. The I/O processing is commenced byan interrupt through a data enable signal of the A/D converter 3 andserves to temporarily transfer input data from the A/D converter 3 to abuffer 51 indicated as an area in the memory 5 in FIG. 2. A semaphoreserving as a real-time monitor also may be set up in the buffer 51.Then, when data to be processed exists in the buffer 51, the DSP 2synchronizes with the data based upon the semaphore value and transfersthe data to a signal processing task which is waiting for the data.

However, since this method requires interrupt processing for receivinginput data from A/D converter 3, it usually increases the processor loadin the DSP 2. For example, the data receiving operation of the DSP 2from the A/D converter 3 is executed through an interrupt and makes itimpossible for the DSP 2 to carry out other processing such ashigh-speed computing operations during the execution of the aboveprocessing. The processing capability of the DSP 2 is thereby greatlyrestricted.

In addition, if it takes longer for the DSP 2 to process I/O data thanthe I/O period of the I/O device, some data may be left behind after theprocessing. Accordingly, the data I/O period of the I/O device isrestricted by the DSP 2 processing speed. For example, the sampling rateof the A/D converter 3 such as shown in FIG. 2 or a generation rate ofthe D/A converter is restricted by the processing speed of the DSP 2.Therefore, this method has a disadvantage that the I/O device speedcannot be increased beyond the speed of the DSP 2.

In view of the above restriction, when implementing the method (2) usinga circuit as shown in FIG. 3, the I/O processing is not carried out as adifferent task but is carried out with an instruction contained in asignal processing task. According to this method, an external registerfile 9 is provided between the A/D converter 3 and the DSP 2 andperforms the synchronization of the data without a real-time monitor.That is, this method does not use an interrupt to communicate with themonitor program. Instead, the register file 9 performs an I/O dataoperation in response to a read/write command in a task for a series ofsignal processing tasks until it reaches the I/O limitation of theregister file 9. Such an I/O limitation includes the operation period ofthe I/O device.

In actual operation, the DSP 2 checks the contents of the register file9 to ascertain whether data exists in the register file 9. If there isno data in the register file 9, the DSP 2 is placed in a waiting stateso that it is not required to carry out another process such as checkingthe content of the semaphore in accordance with method (1). Since theDSP 2 accesses the I/O devices through the register file 9, the DSP 2requires no interrupt processing. Thus, the burden imposed on the DSP 2in association with the data I/O processing can be alleviated.

However, this method has a disadvantage that during this waiting state,the DSP 2 still cannot carry out any other processing, which results inprocessing overhead. Thus, the total processing efficiency of the systemis reduced due to processing overhead. This method has a furtherdisadvantage that the register file 9 is comprised of expensive hardwarewhich increases the total cost of the system. Moreover, many registerfiles are sometimes required for one system so that this method resultsin a large increase in the total manufacturing cost for the system.Further, when the data input and output period exceeds the processingperiod of the DSP 2, the input data to the register file 9 isoverflowed, and thus, some data may be lost.

SUMMARY OF THE INVENTION

This invention has been made to overcome the above disadvantages of theprior art. It is an object of the current invention to access datawithout data loss even when the I/O period in the external I/O device isshorter than the data processing period of the DSP. It is another objectof the invention to successively process the data so as to preventprocessing overhead when the I/O period is longer than the DSPprocessing period. It is yet another object of the current invention toprovide a control method for a digital signal processing system capableof realizing the above operations at a lower cost than comparable priorart devices.

According to the current invention, when the I/O period of an externalI/O device is shorter than the DSP processing period, the data receptionand transmission to and from external I/O devices such as an A/Dconverter, a D/A converter and so on are performed through a DMAcontroller between a memory and the external I/O devices. In oneembodiment, the DMA controller is used to perform the data processingwhich is to be originally performed by the DSP such that the data I/Oprocessing is carried out independently of the calculations by the DSPwhereby the burden of the DSP is alleviated. In addition, since the I/Odata can be subject to processing at the maximal transfer rate of theDMA controller, this invention is applicable to a high-speed I/O device.In other cases, the data reception and transmission to and from theexternal I/O devices are directly carried out between the DSP and theexternal I/O devices without the DMA controller.

In accordance with the invention, a host CPU calculates the periodrequired for the processing by the DSP. The CPU then compares thisperiod with the I/O period of the external I/O device and determineswhether the data reception and transmission to and from the external I/Odevices is to be carried out through the DMA controller or to bedirectly carried out by the DSP.

In accordance with the invention, in place of a register file, aninexpensive DMA controller is used which is about 1/10 of the cost ofthe register file. Thus, the total manufacturing cost of the system isgreatly decreased.

The DSP of the invention may also execute a data empty check programusing a semaphore to determine the existence of I/O data in an inputbuffer of the DSP. This program prevents the DSP itself from fallinginto a waiting state for the I/O data. Thus, during the data emptystate, the DSP can carry out other processing without waiting.

The invention is further characterized by the execution of a DSP programwhich comprises at least one process having I/O parameters and a datareception and transmission addresses which are provided to the I/Oparameters during the execution of each process. That is, in eachprocess an address for an external I/O device such as a memory, a latchand the like is provided through the I/O parameters by merely invokingthe processing function for the process. It is thus unnecessary to writeinstructions for accessing hardware such as the memory and the externalI/O devices for each access. Customized programming for different kindsof external I/O devices is also eliminated by merely providingappropriate I/O addresses to the DSP processes via the I/O parameters.In addition, a signal processing program for one system is easilytransported to another system so as to more effectively use a softwareresource.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a conventional multi-processor type digital signalprocessing system.

FIG. 2 shows a conventional digital signal processing system usinginterrupts.

FIG. 3 shows a conventional digital signal processing system using anexternal register file.

FIG. 4 shows an embodiment of a digital signal processing system inaccordance with the invention in which the control method of theinvention is implemented.

FIG. 5 is a block flow diagram showing an embodiment of the controlmethod for use in the digital signal processing system as shown in FIG.4.

FIG. 6 is a data flow diagram showing an embodiment of the controlmethod for use in the digital signal processing system as shown in FIG.4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 4 shows an embodiment of a control system for a digital signalprocessing system according to the invention. In FIG. 4, the CPU 1 andthe whole system including the DSP 2 (such as the DSP 96002 produced byMotorola Company), the external I/O devices (such as A/D converter 3 andperipheral I/O interface 4), and the memory 5 with a real-time monitorare connected to one another through the common buses including data bus6 and address bus 7. A decoder 8 for outputting a control signal to theA/D converter 3 is provided on the address bus 7. In addition, a latch 9is provided in place of the register file as shown in FIG. 3. A directmemory access (DMA) controller 10 is also provided between the data bus6 and the address bus 7. For the purpose of simplicity, the signalprocessing system of FIG. 4 illustrates only one of the DSP units asshown in FIG. 1, and other units are omitted from the figure. As shownin FIGS. 5 and 6, plural signal processing blocks are preferably in thememory 5 so that these blocks constitute a single processing task.

According to the invention, the digital signal processing system isconstructed as illustrated in FIG. 4. However, in accordance with theinvention, either the DMA controller 10 or the DSP 2 are accessed by theA/D converter 3 during data transfer based on the comparison between theI/O period (T_(io)) of the A/D converter 3 and the executing time of aseries of signal processing blocks of the DSP 2, that is, a signalprocessing period (T_(cal)) of the DSP 2. When T_(io) <T_(cal), the I/Operiod T_(io) of the A/D converter 3 is shorter than the signalprocessing period T_(cal) of the DSP 2. Hence, if the signal processingblock required direct data access to the A/D converter 3, some datawould be lost. Accordingly, in this case, the DMA controller 10 is usedand the data I/O operation is independently performed from theprocessing by the series of signal processing blocks. This state will behereinafter referred to as the "first mode." The maximum value of T_(io)is approximately about 1 million words/second in a preferred embodiment.For example, when T_(io) is equal to 800,000 words/second, arelationship of 1/T_(io) >1/T_(cal) can be satisfied (although dependenton the value of T_(cal)). Within a permissible depth of the memorybuffer 51 where the I/O data is stored, the DMA controller 10 performsthe I/O operation independent of DSP 2.

As described above with respect to FIG. 2, when the DSP 2 receives theI/O data from the A/D converter 3, the data receiving operation of theDSP 2 is not typically carried out as an independent task. Instead, theoperation is carried out through the buffer 51 under the control of areal-time monitor. Further, a semaphore is provided in the buffer 51 towhich the input data is stored, and the DSP 2 transfers the data to thesignal processing task while it executes an empty check job to determinewhether the input data is stored in the buffer 51 or not.

On the other hand, when T_(io) ≧T_(cal), the signal processing periodT_(cal) of the DSP 2 is shorter than or equal to the input period T_(io)of the A/D converter 3. Hence, if the signal processing block requiresthe direct I/O data access with the A/D converter 3, no data is lost.This signal processing block is thus commenced through an interruptprocessing by a scheduler or a data ready signal from the A/D converter3. Thus, the processing is carried out without the DMA controller 10.This state will be referred to as the "second mode."

However, as described below, T_(cal) is calculated on the basis of thetime obtained for a series of processing blocks and an error may be madein the calculation when T_(io) ≈T_(cal). Thus, in order to ensure thereliability of the processing operation, even if the signal processingperiod of the DSP is shorter than the sampling period of the A/Dconverter 3, the access to the A/D converter 3 is carried out throughthe DMA controller 10 in the same manner as described above. Hence inthis case, the processing mode of the DSP 2 is set to the first mode asdescribed above. The signal processing task is then controlled so as tobe brought into the waiting state for transmission of the input datainto the buffer 51 even if there are no data in the buffer 51. Thecalculation of the periods T_(io) and T_(cal) and the comparison thereofwill be described in more detail below.

While T_(io) is determined by a host controller such as CPU 1 at thetime when the hardware such as A/D converter 3 for receiving the I/Odata is controlled, T_(cal) is calculated by combining the processingtimes of each block required for processing the data. Then, T_(io) iscompared with T_(cal) by the host CPU 1. The first or second mode asdescribed above is then selected prior to the execution of the signalprocessing program.

Just prior to interrupting DSP 2, the peripheral I/O interface 4 outputsa data ready or data empty signal for every transmission of data.Thereafter, these signals are supplied to the interrupt processingprogram to keep the peripheral I/O interface 4 in synchronism with thesignal processing task which accesses the data in the peripheral I/Ointerface 4.

The program of the signal processing task of the DSP 2 will be now bedescribed. At first, just like supplying an address to the memory 5,addresses are assigned to the external devices such as the A/D converter3, the peripheral I/O interface 4 and the like. These addresses aredelivered to an I/O processing block. In this manner, each external I/Odevice is accessed like a function.

Actually, as shown in the block flow diagram of FIG. 5 and the data flowdiagram of FIG. 6, a series of predetermined signal processing functionsin the DSP 2 are preset so as to access all the I/O data with a pointerin front of and behind the body of the functions. For instance, aspreprocessing for each of processes 21 through 23, or as processingprior to the execution of the first process 21, a function with commonI/O is executed to associate an input and output address of each processrespectively with common parameters "input" and "output." Therefore,using these "input" and "output" parameters as pointers, the signalprocessing function can be expressed as:

    func X (input, output)

    (X=1,2,3).

The above "input" and "output" parameters can be treated in the same wayas a memory.

In a case where an object to be accessed is an I/O device (for example,A/D converter for the data reception of the process 21), duringpreprocessing either the first mode involving processing through the DMAcontroller 10 or the second mode involving processing through the DSP 2itself is selected for accessing the A/D converter 3 based upon acomparison between T_(io) and T_(cal). Thereafter, the address of alatch 9 is given to the "input" pointer and "func 1" is commencedsimultaneously with the reception of the data. Next, when an object tobe accessed is the memory 5, after the calculation in process 21 theaddress of the memory 5 is given to the "output" pointer. Then theseparation of the DMA controller 10 of FIG. 4 is carried out aspostprocessing.

When the memory 5 is to receive the data as in the case of process 22,the wait processing is carried out using the semaphore. The addressthereof is given to the "input" pointer. In the same manner as theprocess 211 "func 2" is commenced simultaneously with the data receptionto deliver the address of the data transmission side to the "output"pointer. "Func 2" transmits the data to the memory 5 after theprocessing by process 22.

Further, when the memory 5 is the data transmission side as in process23, in the same manner as the process 22, the wait processing is carriedout by using the semaphore to deliver the address to the "input" pointerand "func 3" commences. However, in this case, the peripheral I/Ointerface 4 is the data transmission side. Thus, during preprocessing,the peripheral I/O interface 4 is set as an object to be accessed, andthe I/O connection is released during postprocessing.

The processes 21 through 23 perform as described above. When a functionis actually executed in these processes, the external devices to beaccessed such as the A/D converter 3, the memory 5, the peripheral I/Ointerface 4 and the like are specified with the address either as inputor output. Therefore, the signal processing can be performed by thefunction without consideration of the additional input and outputprocessing by specification of the external devices and addresses.

The invention described herein has the following advantages.

(1) Since the data transmission is processed either by the DMAcontroller or the DSP based upon a comparison of the I/O period of theexternal I/O device with the processing period of the signal processingby the DSP, it is possible to realize a control method suitable for allsignals of any periods. In addition, since no external register file isused, the manufacturing cost of the system is reduced.

(2) If the data I/O period of the external I/O device such as the A/Dconverter, the D/A converter and the like is shorter than the processingperiod of the DSP, the data reception and transmission are performedthrough the DMA controller so that the input and output operations canbe completely finished without a data loss even with a high-speedexternal I/O device. Thus, the data processing is carried out withoutreducing the sampling rate of the A/D converter, the generation rate ofthe D/A converter, and the like.

(3) When the I/O period of the external I/O device is longer than theprocessing period of the signal processing task of the DSP, processingoverhead can be reduced. The time saved by reducing the overhead can beused for other processing. Thus, more complicated processing whichotherwise would not be executed in the conventional method may beperformed.

(4) In the data transmission using the DMA controller, if the I/O periodof the external I/O device is substantially longer than the processingperiod of the signal processing task by the DSP, no waiting is requiredat the data input time. Unfortunately, in order to precisely measurethese periods complicated hardware has been required. However, accordingto this invention, the same principle as used in the case where the I/Operiod is shorter than the processing period by DSP is applicable tothis case. Thus, the wait processing using the semaphore is alsoperformed. Therefore, complicated hardware and software for performingthe above measurement is not necessary.

(5) Since the addresses of the external I/O devices such as the A/D orD/A converters, the peripheral I/O interface and the like are associatedwith the I/O parameters in advance and these I/O parameters are servedas the pointers to access the external devices, the data transferbetween the processes can be made in common. Consequently, whenprogramming in a language such as assembler, the specification of theexternal devices and the addresses thereof are not required.Accordingly, the signal processing program can be improved withoutrelying on the hardware. The program thus may be commonly used to reducethe development cost.

What is claimed is:
 1. A signal processing apparatus comprising:memorymeans for storing digital signals and processes for processing saiddigital signals; input and output (I/O) means for inputting andoutputting said digital signals to and from said signal processingapparatus; a direct memory access (DMA) controller connected to saidmemory means and said I/O means for storing/reading said digital signalsto/from said memory means and said I/O means in a direct memory accessmode; a digital signal processor (DSP) connected to said DMA controller,said I/O means, and said memory means for processing said digitalsignals stored in said memory means, said DSP executing a data emptycheck program under the control of a real-time monitor including asemaphore for checking for the existence of said digital signals to beprocessed and executing another process when said digital signals arenot available for processing; and a host CPU connected to said DMA andsaid DSP for determining whether a data transfer requested by a task ofsaid processes is performed by said DMA controller or said DSP basedupon a comparison between an I/O data period and a processing time ofsaid task, whereby said data transfer requested by said task isperformed by said DMA when said I/O period is shorter than saidprocessing time of said task.
 2. Apparatus according to claim 1 whereinsaid DSP uses an interrupt for initiating data transfer with said I/Omeans when said processing time of said task is shorter than said I/Operiod.
 3. Apparatus according to claim 1 wherein address of said I/Omeans are passed between said processes as input and output parametersin a process function call.
 4. A method of processing digital signals ina signal processing apparatus comprising an input and output (I/O)means, memory means for storing said digital signals and a plurality ofprocesses which operate on said digital signals, a direct memory access(DMA) controller, and a digital signal processor (DSP) for processingsaid digital signals stored in said memory means for digital signalsreceived directly from said I/O means in accordance with a data transferrequest from said plurality of processes, said method comprising thesteps of:a) executing a data empty check program on said DSP using areal-time monitor including a semaphore for checking for the existenceof said digital signals to be processed and executing another processwhen said digital signals are not available for processing; b)determining a processing period of a task processing said digitalsignals; c) determining an I/O period; d) comparing said processingperiod to said I/O period; e) invoking said DMA controller fortransferring said digital signals to/from said memory means based uponsaid comparison in step c) when said processing period is longer thansaid I/O period; f) interrupting said DSP currently processing saiddigital signals based upon said comparison in step c) to initiate an I/Odata transfer when said processing period is shorter than said I/Operiod; and g) continuing processing of said digital signals inaccordance with said plurality of processes stored in said memory means.5. Method according to claim 5 comprising the further step of passingaddresses of said I/O means between said processes as input and outputparameters in a process function call.